Power FPSCR Register
For your convenience, TotalView interprets the bit settings of the Power FPSCR register. You can edit the value of the FPSCR and set it to any of the bit settings outlined in the following table.
On this page:
Bit Settings
|
Value |
Bit Setting |
Meaning |
|
0x80000000 |
FX |
Floating-point exception summary |
|
0x40000000 |
FEX |
Floating-point enabled exception summary |
|
0x20000000 |
VX |
Floating-point invalid operation exception summary |
|
0x10000000 |
OX |
Floating-point overflow exception |
|
0x08000000 |
UX |
Floating-point underflow exception |
|
0x04000000 |
ZX |
Floating-point zero divide exception |
|
0x02000000 |
XX |
Floating-point inexact exception |
|
0x01000000 |
VXSNAN |
Floating-point invalid operation exception for SNaN |
|
0x00800000 |
VXISI |
Floating-point invalid operation exception: ¥ - ¥, or infinity‑infinity |
|
0x00400000 |
VXIDI |
Floating-point invalid operation exception: ¥ / ¥, or infinity divided by infinity |
|
0x00200000 |
VXZDZ |
Floating-point invalid operation exception: 0 / 0 |
|
0x00100000 |
VXIMZ |
Floating-point invalid operation exception: ¥ * ¥, or infinity times infinity |
|
0x00080000 |
VXVC |
Floating-point invalid operation exception: invalid compare |
|
0x00040000 |
FR |
Floating-point fraction rounded |
|
0x00020000 |
FI |
Floating-point fraction inexact |
|
0x00010000 |
FPRF=(C) |
Floating-point result class descriptor |
|
0x00008000 |
FPRF=(L) |
Floating-point less than or negative |
|
0x00004000 |
FPRF=(G) |
Floating-point greater than or positive |
|
0x00002000 |
FPRF=(E) |
Floating-point equal or zero |
|
0x00001000 |
FPRF=(U) |
Floating-point unordered or NaN |
|
0x00011000 |
FPRF=(QNAN) |
Quiet NaN; alias for FPRF=(C+U) |
|
0x00009000 |
FPRF=(-INF) |
-Infinity; alias for FPRF=(L+U) |
|
0x00008000 |
FPRF=(-NORM) |
-Normalized number; alias for FPRF=(L) |
|
0x00018000 |
FPRF=(-DENORM) |
-Denormalized number; alias for FPRF=(C+L) |
|
0x00012000 |
FPRF=(-ZERO) |
-Zero; alias for FPRF=(C+E) |
|
0x00002000 |
FPRF=(+ZERO) |
+Zero; alias for FPRF=(E) |
|
0x00014000 |
FPRF=(+DENORM) |
+Denormalized number; alias for FPRF=(C+G) |
|
0x00004000 |
FPRF=(+NORM) |
+Normalized number; alias for FPRF=(G) |
|
0x00005000 |
FPRF=(+INF) |
+Infinity; alias for FPRF=(G+U) |
|
0x00000400 |
VXSOFT |
Floating-point invalid operation exception: software request |
|
0x00000200 |
VXSQRT |
Floating-point invalid operation exception: square root |
|
0x00000100 |
VXCVI |
Floating-point invalid operation exception: invalid integer convert |
|
0x00000080 |
VE |
Floating-point invalid operation exception enable |
|
0x00000040 |
OE |
Floating-point overflow exception enable |
|
0x00000020 |
UE |
Floating-point underflow exception enable |
|
0x00000010 |
ZE |
Floating-point zero divide exception enable |
|
0x00000008 |
XE |
Floating-point inexact exception enable |
|
0x00000004 |
NI |
Floating-point non-IEEE mode enable |
|
0x00000000 |
RN=NEAR |
Round to nearest |
|
0x00000001 |
RN=ZERO |
Round toward zero |
|
0x00000002 |
RN=PINF |
Round toward +infinity |
|
0x00000003 |
RN=NINF |
Round toward -infinity |
Using the Power FPSCR Register
On AIX, if you compile your program to catch floating-point exceptions (IBM compiler -qflttrap option), you can change the value of the FPSCR within TotalView to customize the exception handling for your program.
For example, if your program inadvertently divides by zero, you can edit the bit setting of the FPSCR register in the Registers View. In this case, you would change the bit setting for the FPSCR to include 0x10 so that TotalView traps the “divide by zero” exception. The string displayed next to the FPSR register should now include ZE. Now, when your program divides by zero, it receives a SIGTRAP signal, which will be caught by TotalView. See Signal Actions for more information. If you did not set the bit for trapping divide by zero or you did not compile to catch floating-point exceptions, your program would not stop and the processor would set the ZX bit.