Totalview® Reference Guide : PART III Platforms and Operating Systems : Chapter 11 Architectures : Power Architectures : Power MSR Register
Power MSR Register
For your convenience, TotalView interprets the bit settings of the Power MSR register. You can edit the value of the MSR and set it to any of the bit settings outlined in the following table.
Value
Bit Setting
Meaning
0x80000000000000000
SF
Sixty-four bit mode
0x0000000000040000
POW
Power management enable
0x0000000000020000
TGPR
Temporary GPR mapping
0x0000000000010000
ILE
Exception little-endian mode
0x0000000000008000
EE
External interrupt enable
0x0000000000004000
PR
Privilege level
0x0000000000002000
FP
Floating-point available
0x0000000000001000
ME
Machine check enable
0x0000000000000800
FE0
Floating-point exception mode 0
0x0000000000000400
SE
Single-step trace enable
0x0000000000000200
BE
Branch trace enable
0x0000000000000100
FE1
Floating-point exception mode 1
0x0000000000000040
IP
Exception prefix
0x0000000000000020
IR
Instruction address translation
0x0000000000000010
DR
Data address translation
0x0000000000000002
RI
Recoverable exception
0x0000000000000001
LE
Little-endian mode enable