The descriptions in this section are taken (almost verbatim) from the “Intel Itanium Architecture Software Developer’s Manual. Volume 1: Application Architecture”. This was revision 2.0, printed in December 2001.The descriptions in this section are taken (almost verbatim) from the “Intel Itanium Architecture Software Developer’s Manual. Volume 1: Application Architecture”. This was revision 2.0, printed in December 2001.Register | Description | Data Type | Edit | Dive | in expression |
r0 | register 0 | $long | N | Y | $r0 |
r1 | global pointer | $long | N | Y | $r1 |
r2-r31 | static general registers | $long | Y | Y | $r2-$r31 |
r31-r127 | stacked general registers (all may not be valid) | $long | Y | Y | $r32-$r127 |
b0-b7 | branch registers | $code[] | Y | Y | $b0-$b7 |
ip | instruction pointer | $code[] | N | Y | $ip |
cfm | current frame marker | $long | Y | Y | $cfm |
psr | processor status register | $long | Y | Y | $psr |
rsc | register stack configuration register (AR 16) | $long | Y (N on HP-UX) | Y | $rsc |
bsp | rse backing store pointer (AR 17) | $long | Y | Y | $bsp |
bspstore | rse backing store pointer for memory stores (AR 18) | $long | N | Y | $bspstore |
rnat | rse NAT collection register (AR 19) | $long | Y | Y | $rnat |
ccv | compare and exchange value register (AR 32) | $long | Y | Y | $ccv |
unat | user NAT collection register (AR 36) | $long | Y | Y | $unat |
fpsr | floating point status register (AR 40) | $long | Y | Y | $fpsr |
pfs | previous function state (AR 64) | $long | Y | Y | $pfs |
lc | loop count register (AR 65) | $long | Y | Y | $lc |
ec | epilog count register (AR 66) | $long | Y | Y | $ec |
pr | predication registers (packed) | $long | Y | Y | $pr |
nat | nat registers (packed) | $long | Y | Y | $nat |
All general registers r32-r127 may not be valid in a given stack frame.