Totalview® for HPC Reference Guide : PART III Platforms and Operating Systems : Chapter 11 Architectures : Sun SPARC : SPARC FPSR Register : Using the SPARC FPSR Register
Using the SPARC FPSR Register
The SPARC processor does not catch floating-point errors by default. You can change the value of the FPSR within TotalView to customize the exception handling for your program.
For example, if your program inadvertently divides by zero, you can edit the bit setting of the FPSR register in the Stack Frame Pane. In this case, you would change the bit setting for the FPSR to include 0x01000000 so that TotalView traps the “divide by zero” bit. The string displayed next to the FPSR register should now include TEM=(DZ). Now, when your program divides by zero, it receives a SIGFPE signal, which you can catch with TotalView. See “Handling Signals” for more information. If you did not set the bit for trapping divide by zero, the processor would ignore the error and set the AEXC=(DZ) bit.