Totalview® for HPC Reference Guide : PART III Platforms and Operating Systems : Chapter 11 Architectures : Power Architectures : Power FPSCR Register : Using the Power FPSCR Register
Using the Power FPSCR Register
On AIX, if you compile your program to catch floating-point exceptions (IBM compiler -qflttrap option), you can change the value of the FPSCR within TotalView to customize the exception handling for your program.
For example, if your program inadvertently divides by zero, you can edit the bit setting of the FPSCR register in the Stack Frame Pane. In this case, you would change the bit setting for the FPSCR to include 0x10 so that TotalView traps the “divide by zero” exception. The string displayed next to the FPSR register should now include ZE. Now, when your program divides by zero, it receives a SIGTRAP signal, which will be caught by TotalView. See “Handling Signals” for more information. If you did not set the bit for trapping divide by zero or you did not compile to catch floating-point exceptions, your program would not stop and the processor would set the ZX bit.